1. Field of the Invention
This invention relates to electrical circuits useful in diagnosing faults in digital systems, and more particularly, for diagnosing faults by serial scan techniques.
2. Prior Art
A digital system may often be generalized into a system of logic blocks. The logic blocks, which may consist of a large number of logic gates performing complicated functions, operate on sets of parallel data and control signals. The signals enter a particular logic block, are transformed, and leave the logic block for the next logic block. The data travel through the logic blocks of the system until they exist as the desired output data of the system.
Signal paths for the electrical control and data signals connect the logic blocks. Registers are usually located in these signal paths to temporarily hold the digital signals from one logic block and to release the data to the next logic block at the proper time. The data may also be released as feedback to logic blocks "upstream". Registers permit the proper coordination of data movement through the system.
In these systems the testing and diagnosing of faults becomes a problem. If a failure occurs at some point within the system and only the input and output ports of the system are available for testing, then the isolation of the failure becomes very difficult. For example, any test input data must pass through logic blocks 1 and 2 before the data can be used to test the logic in block 3. Any failure in these earlier logic blocks cause the data to be unusable for testing later logic blocks. Even if logic "upstream" from the failure functions correctly, the test output data may be ruined by an intervening failure. The fault with this type of system organization is that hardware failures may be detected but not located.
Isolation of faults is possible if intermediate test points are available and various designs have been proposed. One technique which is used to provide these intermediate test points is the serial scan technique. A generalized digital system, as discussed previously, is shown in FIG. 1. The system is modified so that serial scan diagnosis is possible. As in a generalized system, the data and control signals move from logic block to logic block along signal path 11. Shift registers 12, 16, 20 maintain the timing of signal movement. However, the registers are modified so that they can operate in two modes. In the normal mode the registers pass signals in parallel from one logic block to another. In the diagnostic mode the registers operate as serial shift registers by which test data may be shifted into the register. Then the registers in normal mode release the test data into the logic blocks to be operated upon. The test data is then read out by the registers receiving the test output data for examination of faults. For example, logic block 2 in FIG. 1 may be examined by the serial introduction of test data into the register 12, passing the data through logic block 2 and serially removing the test data by the register 16.
A variation of the serial scan technique has the serial output line connected to the serial input line of a succeeding register. A string of test data is scanned into the registers, which are then set to operate in normal mode. After the logic blocks operate on the test data from the registers, the test data is scanned out in a string to determine whether faults exist in the different logic blocks. Other variations of the serial scan technique are possible. All of these variations reduce the number of test-fix iterations necessary to repair or debug a system for a corresponding reduction in cost.
However, the simple serial scan register circuit of FIG. 1 has problems, one of which may occur when the register is in the control path of the system, such as a microinstruction register of a processor. In such a register, certain data combinations at certain bit positions may be forbidden. This forbidden conditions may be violated as the data information is scanned in or out of the serial shift register.
For example, a typical field in a microinstruction register could include a series of enable bits to enable buffers onto a bus. If serial test data is shifted through this microinstruction register, a condition could result which is illegal in normal execution (a restriction is put on the control flow such that only one bit can be low, or enabled, at a time). This illegal combination results in overstressing the devices and could seriously damage the associated circuitry.
Other problems result in latched systems and asynchronous systems. In an asynchronous system, if one of the outputs, or a logical combinations of outputs, of the shift register is used to generate a signal to an asynchronous (unclocked) subsystem, such as a memory or input/output device, an unwanted access to the subsystem may be generated when the register is shifted for test operations. This could result in an unpredictable disruption of the system state, making fault isolation much more difficult.
In a latched system, the register used as a microinstruction register and having its bit outputs, or logical combinations thereof, setting, resetting or opening latches in the system causes problems also. Test data shifted through the register may disturb the system state. This type of problem is especially serious when the latch contents cannot be re-established, making additional testing virtually impossible.
The present invention solves or substantially mitigates these problems and is a substantial advancement over the simple serial scan register. A circuit is provided by which data may be serially introduced into and removed from a signal path for the testing of the integrity of the digital system. The circuit has a minimum number of control lines to achieve a savings in economy, yet retains ample control functions for flexibility.